Modern integrated circuits (ICs) exhibit large amounts of variability in their performance because of variations in manufacturing processes and environmental parameters. The range of these variations defines a process space, and at differing points in the process space differing timing paths may be critical. One approach for testing timing path criticality is to test all timing paths for all possible combination of timing-influencing parameters. However, as integration scale continues to grow, the number of timing paths in a particular IC design increases, and this approach becomes impractical to implement. Therefore, a challenge exists for testing ICs in a manner that provides broad test coverage of the process space in a reasonable amount of time.
Current IC testing approaches may include, for example, at-speed functional testing on a tester and/or functional test in a system. However, these approaches typically require expensive test systems and intensive manual effort. Furthermore, the test coverage cannot be accurately measured. Another approach to testing ICs is transition-fault testing based on tester clocks. However, such tests do not exercise the functional clock tree on the chip, do not test paths in a functional manner, and do not detect small delay defects on paths that are affected by process variations. Yet another approach to testing ICs is path-delay testing based on static timing analysis (STA). However, STA produces many false or Boolean unsensitizable paths. Furthermore, STA is not accurate in uncovering paths that are affected by process variations. Consequently, process coverage is poor using path delay testing based on STA. Yet another approach to testing ICs is to perform at-speed structural testing (ASST) to test transition faults without respect to critical paths. However, ASST may not exercise critical paths and, hence, performance validation is not achieved.